Nano Structure Patterning By Standard CMOS Technology Process
tm3003911010
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The realization of reliable nano devices requires the improvement of fabrication techniques to form the nanometer-sized structures and pattern. Organizing these nano structures can be fabricated with a combination of lithography and etching techniques. However, these patterning technology encounters many challenges which arise from not only cost and time but also compatibility of current technology.
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Institute of Nano Electronic Engineering (INEE), Universiti Malaysia Perlis (UniMAP),
P.O. Box 77, D/a Pejabat Pos Besar
01000 Kangar
Perlis
Malaysia
Full Name [1]
Prof. Dr. Uda Hashim
Email [1]
uda@unimap.edu.my
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